// Peripheral: TSC_Periph  Touch Sensing Controller (TSC).
// Instances:
//  TSC  mmap.TSC_BASE
// Registers:
//  0x00 32  CR        Control register.
//  0x04 32  IER       Interrupt enable register.
//  0x08 32  ICR       Interrupt clear register.
//  0x0C 32  ISR       Interrupt status register.
//  0x10 32  IOHCR     I/O hysteresis control register.
//  0x18 32  IOASCR    I/O analog switch control register.
//  0x20 32  IOSCR     I/O sampling control register.
//  0x28 32  IOCCR     I/O channel control register.
//  0x30 32  IOGCSR    I/O group control status register.
//  0x34 32  IOGXCR[8] I/O group x counter register.
// Import:
//  stm32/o/f303xe/mmap
package tsc

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	TSCE    CR = 0x01 << 0  //+ Touch sensing controller enable.
	START   CR = 0x01 << 1  //+ Start acquisition.
	AM      CR = 0x01 << 2  //+ Acquisition mode.
	SYNCPOL CR = 0x01 << 3  //+ Synchronization pin polarity.
	IODEF   CR = 0x01 << 4  //+ IO default mode.
	MCV     CR = 0x07 << 5  //+ MCV[2:0] bits (Max Count Value).
	PGPSC   CR = 0x07 << 12 //+ PGPSC[2:0] bits (Pulse Generator Prescaler).
	SSPSC   CR = 0x01 << 15 //+ Spread Spectrum Prescaler.
	SSE     CR = 0x01 << 16 //+ Spread Spectrum Enable.
	SSD     CR = 0x7F << 17 //+ SSD[6:0] bits (Spread Spectrum Deviation).
	CTPL    CR = 0x0F << 24 //+ CTPL[3:0] bits (Charge Transfer pulse low).
	CTPH    CR = 0x0F << 28 //+ CTPH[3:0] bits (Charge Transfer pulse high).
)

const (
	TSCEn    = 0
	STARTn   = 1
	AMn      = 2
	SYNCPOLn = 3
	IODEFn   = 4
	MCVn     = 5
	PGPSCn   = 12
	SSPSCn   = 15
	SSEn     = 16
	SSDn     = 17
	CTPLn    = 24
	CTPHn    = 28
)

const (
	EOAIE IER = 0x01 << 0 //+ End of acquisition interrupt enable.
	MCEIE IER = 0x01 << 1 //+ Max count error interrupt enable.
)

const (
	EOAIEn = 0
	MCEIEn = 1
)

const (
	EOAIC ICR = 0x01 << 0 //+ End of acquisition interrupt clear.
	MCEIC ICR = 0x01 << 1 //+ Max count error interrupt clear.
)

const (
	EOAICn = 0
	MCEICn = 1
)

const (
	EOAF ISR = 0x01 << 0 //+ End of acquisition flag.
	MCEF ISR = 0x01 << 1 //+ Max count error flag.
)

const (
	EOAFn = 0
	MCEFn = 1
)

const (
	G1_IO1 IOHCR = 0x01 << 0  //+ GROUP1_IO1 schmitt trigger hysteresis mode.
	G1_IO2 IOHCR = 0x01 << 1  //+ GROUP1_IO2 schmitt trigger hysteresis mode.
	G1_IO3 IOHCR = 0x01 << 2  //+ GROUP1_IO3 schmitt trigger hysteresis mode.
	G1_IO4 IOHCR = 0x01 << 3  //+ GROUP1_IO4 schmitt trigger hysteresis mode.
	G2_IO1 IOHCR = 0x01 << 4  //+ GROUP2_IO1 schmitt trigger hysteresis mode.
	G2_IO2 IOHCR = 0x01 << 5  //+ GROUP2_IO2 schmitt trigger hysteresis mode.
	G2_IO3 IOHCR = 0x01 << 6  //+ GROUP2_IO3 schmitt trigger hysteresis mode.
	G2_IO4 IOHCR = 0x01 << 7  //+ GROUP2_IO4 schmitt trigger hysteresis mode.
	G3_IO1 IOHCR = 0x01 << 8  //+ GROUP3_IO1 schmitt trigger hysteresis mode.
	G3_IO2 IOHCR = 0x01 << 9  //+ GROUP3_IO2 schmitt trigger hysteresis mode.
	G3_IO3 IOHCR = 0x01 << 10 //+ GROUP3_IO3 schmitt trigger hysteresis mode.
	G3_IO4 IOHCR = 0x01 << 11 //+ GROUP3_IO4 schmitt trigger hysteresis mode.
	G4_IO1 IOHCR = 0x01 << 12 //+ GROUP4_IO1 schmitt trigger hysteresis mode.
	G4_IO2 IOHCR = 0x01 << 13 //+ GROUP4_IO2 schmitt trigger hysteresis mode.
	G4_IO3 IOHCR = 0x01 << 14 //+ GROUP4_IO3 schmitt trigger hysteresis mode.
	G4_IO4 IOHCR = 0x01 << 15 //+ GROUP4_IO4 schmitt trigger hysteresis mode.
	G5_IO1 IOHCR = 0x01 << 16 //+ GROUP5_IO1 schmitt trigger hysteresis mode.
	G5_IO2 IOHCR = 0x01 << 17 //+ GROUP5_IO2 schmitt trigger hysteresis mode.
	G5_IO3 IOHCR = 0x01 << 18 //+ GROUP5_IO3 schmitt trigger hysteresis mode.
	G5_IO4 IOHCR = 0x01 << 19 //+ GROUP5_IO4 schmitt trigger hysteresis mode.
	G6_IO1 IOHCR = 0x01 << 20 //+ GROUP6_IO1 schmitt trigger hysteresis mode.
	G6_IO2 IOHCR = 0x01 << 21 //+ GROUP6_IO2 schmitt trigger hysteresis mode.
	G6_IO3 IOHCR = 0x01 << 22 //+ GROUP6_IO3 schmitt trigger hysteresis mode.
	G6_IO4 IOHCR = 0x01 << 23 //+ GROUP6_IO4 schmitt trigger hysteresis mode.
	G7_IO1 IOHCR = 0x01 << 24 //+ GROUP7_IO1 schmitt trigger hysteresis mode.
	G7_IO2 IOHCR = 0x01 << 25 //+ GROUP7_IO2 schmitt trigger hysteresis mode.
	G7_IO3 IOHCR = 0x01 << 26 //+ GROUP7_IO3 schmitt trigger hysteresis mode.
	G7_IO4 IOHCR = 0x01 << 27 //+ GROUP7_IO4 schmitt trigger hysteresis mode.
	G8_IO1 IOHCR = 0x01 << 28 //+ GROUP8_IO1 schmitt trigger hysteresis mode.
	G8_IO2 IOHCR = 0x01 << 29 //+ GROUP8_IO2 schmitt trigger hysteresis mode.
	G8_IO3 IOHCR = 0x01 << 30 //+ GROUP8_IO3 schmitt trigger hysteresis mode.
	G8_IO4 IOHCR = 0x01 << 31 //+ GROUP8_IO4 schmitt trigger hysteresis mode.
)

const (
	G1_IO1n = 0
	G1_IO2n = 1
	G1_IO3n = 2
	G1_IO4n = 3
	G2_IO1n = 4
	G2_IO2n = 5
	G2_IO3n = 6
	G2_IO4n = 7
	G3_IO1n = 8
	G3_IO2n = 9
	G3_IO3n = 10
	G3_IO4n = 11
	G4_IO1n = 12
	G4_IO2n = 13
	G4_IO3n = 14
	G4_IO4n = 15
	G5_IO1n = 16
	G5_IO2n = 17
	G5_IO3n = 18
	G5_IO4n = 19
	G6_IO1n = 20
	G6_IO2n = 21
	G6_IO3n = 22
	G6_IO4n = 23
	G7_IO1n = 24
	G7_IO2n = 25
	G7_IO3n = 26
	G7_IO4n = 27
	G8_IO1n = 28
	G8_IO2n = 29
	G8_IO3n = 30
	G8_IO4n = 31
)

const (
	G1_IO1 IOASCR = 0x01 << 0  //+ GROUP1_IO1 analog switch enable.
	G1_IO2 IOASCR = 0x01 << 1  //+ GROUP1_IO2 analog switch enable.
	G1_IO3 IOASCR = 0x01 << 2  //+ GROUP1_IO3 analog switch enable.
	G1_IO4 IOASCR = 0x01 << 3  //+ GROUP1_IO4 analog switch enable.
	G2_IO1 IOASCR = 0x01 << 4  //+ GROUP2_IO1 analog switch enable.
	G2_IO2 IOASCR = 0x01 << 5  //+ GROUP2_IO2 analog switch enable.
	G2_IO3 IOASCR = 0x01 << 6  //+ GROUP2_IO3 analog switch enable.
	G2_IO4 IOASCR = 0x01 << 7  //+ GROUP2_IO4 analog switch enable.
	G3_IO1 IOASCR = 0x01 << 8  //+ GROUP3_IO1 analog switch enable.
	G3_IO2 IOASCR = 0x01 << 9  //+ GROUP3_IO2 analog switch enable.
	G3_IO3 IOASCR = 0x01 << 10 //+ GROUP3_IO3 analog switch enable.
	G3_IO4 IOASCR = 0x01 << 11 //+ GROUP3_IO4 analog switch enable.
	G4_IO1 IOASCR = 0x01 << 12 //+ GROUP4_IO1 analog switch enable.
	G4_IO2 IOASCR = 0x01 << 13 //+ GROUP4_IO2 analog switch enable.
	G4_IO3 IOASCR = 0x01 << 14 //+ GROUP4_IO3 analog switch enable.
	G4_IO4 IOASCR = 0x01 << 15 //+ GROUP4_IO4 analog switch enable.
	G5_IO1 IOASCR = 0x01 << 16 //+ GROUP5_IO1 analog switch enable.
	G5_IO2 IOASCR = 0x01 << 17 //+ GROUP5_IO2 analog switch enable.
	G5_IO3 IOASCR = 0x01 << 18 //+ GROUP5_IO3 analog switch enable.
	G5_IO4 IOASCR = 0x01 << 19 //+ GROUP5_IO4 analog switch enable.
	G6_IO1 IOASCR = 0x01 << 20 //+ GROUP6_IO1 analog switch enable.
	G6_IO2 IOASCR = 0x01 << 21 //+ GROUP6_IO2 analog switch enable.
	G6_IO3 IOASCR = 0x01 << 22 //+ GROUP6_IO3 analog switch enable.
	G6_IO4 IOASCR = 0x01 << 23 //+ GROUP6_IO4 analog switch enable.
	G7_IO1 IOASCR = 0x01 << 24 //+ GROUP7_IO1 analog switch enable.
	G7_IO2 IOASCR = 0x01 << 25 //+ GROUP7_IO2 analog switch enable.
	G7_IO3 IOASCR = 0x01 << 26 //+ GROUP7_IO3 analog switch enable.
	G7_IO4 IOASCR = 0x01 << 27 //+ GROUP7_IO4 analog switch enable.
	G8_IO1 IOASCR = 0x01 << 28 //+ GROUP8_IO1 analog switch enable.
	G8_IO2 IOASCR = 0x01 << 29 //+ GROUP8_IO2 analog switch enable.
	G8_IO3 IOASCR = 0x01 << 30 //+ GROUP8_IO3 analog switch enable.
	G8_IO4 IOASCR = 0x01 << 31 //+ GROUP8_IO4 analog switch enable.
)

const (
	G1_IO1n = 0
	G1_IO2n = 1
	G1_IO3n = 2
	G1_IO4n = 3
	G2_IO1n = 4
	G2_IO2n = 5
	G2_IO3n = 6
	G2_IO4n = 7
	G3_IO1n = 8
	G3_IO2n = 9
	G3_IO3n = 10
	G3_IO4n = 11
	G4_IO1n = 12
	G4_IO2n = 13
	G4_IO3n = 14
	G4_IO4n = 15
	G5_IO1n = 16
	G5_IO2n = 17
	G5_IO3n = 18
	G5_IO4n = 19
	G6_IO1n = 20
	G6_IO2n = 21
	G6_IO3n = 22
	G6_IO4n = 23
	G7_IO1n = 24
	G7_IO2n = 25
	G7_IO3n = 26
	G7_IO4n = 27
	G8_IO1n = 28
	G8_IO2n = 29
	G8_IO3n = 30
	G8_IO4n = 31
)

const (
	G1_IO1 IOSCR = 0x01 << 0  //+ GROUP1_IO1 sampling mode.
	G1_IO2 IOSCR = 0x01 << 1  //+ GROUP1_IO2 sampling mode.
	G1_IO3 IOSCR = 0x01 << 2  //+ GROUP1_IO3 sampling mode.
	G1_IO4 IOSCR = 0x01 << 3  //+ GROUP1_IO4 sampling mode.
	G2_IO1 IOSCR = 0x01 << 4  //+ GROUP2_IO1 sampling mode.
	G2_IO2 IOSCR = 0x01 << 5  //+ GROUP2_IO2 sampling mode.
	G2_IO3 IOSCR = 0x01 << 6  //+ GROUP2_IO3 sampling mode.
	G2_IO4 IOSCR = 0x01 << 7  //+ GROUP2_IO4 sampling mode.
	G3_IO1 IOSCR = 0x01 << 8  //+ GROUP3_IO1 sampling mode.
	G3_IO2 IOSCR = 0x01 << 9  //+ GROUP3_IO2 sampling mode.
	G3_IO3 IOSCR = 0x01 << 10 //+ GROUP3_IO3 sampling mode.
	G3_IO4 IOSCR = 0x01 << 11 //+ GROUP3_IO4 sampling mode.
	G4_IO1 IOSCR = 0x01 << 12 //+ GROUP4_IO1 sampling mode.
	G4_IO2 IOSCR = 0x01 << 13 //+ GROUP4_IO2 sampling mode.
	G4_IO3 IOSCR = 0x01 << 14 //+ GROUP4_IO3 sampling mode.
	G4_IO4 IOSCR = 0x01 << 15 //+ GROUP4_IO4 sampling mode.
	G5_IO1 IOSCR = 0x01 << 16 //+ GROUP5_IO1 sampling mode.
	G5_IO2 IOSCR = 0x01 << 17 //+ GROUP5_IO2 sampling mode.
	G5_IO3 IOSCR = 0x01 << 18 //+ GROUP5_IO3 sampling mode.
	G5_IO4 IOSCR = 0x01 << 19 //+ GROUP5_IO4 sampling mode.
	G6_IO1 IOSCR = 0x01 << 20 //+ GROUP6_IO1 sampling mode.
	G6_IO2 IOSCR = 0x01 << 21 //+ GROUP6_IO2 sampling mode.
	G6_IO3 IOSCR = 0x01 << 22 //+ GROUP6_IO3 sampling mode.
	G6_IO4 IOSCR = 0x01 << 23 //+ GROUP6_IO4 sampling mode.
	G7_IO1 IOSCR = 0x01 << 24 //+ GROUP7_IO1 sampling mode.
	G7_IO2 IOSCR = 0x01 << 25 //+ GROUP7_IO2 sampling mode.
	G7_IO3 IOSCR = 0x01 << 26 //+ GROUP7_IO3 sampling mode.
	G7_IO4 IOSCR = 0x01 << 27 //+ GROUP7_IO4 sampling mode.
	G8_IO1 IOSCR = 0x01 << 28 //+ GROUP8_IO1 sampling mode.
	G8_IO2 IOSCR = 0x01 << 29 //+ GROUP8_IO2 sampling mode.
	G8_IO3 IOSCR = 0x01 << 30 //+ GROUP8_IO3 sampling mode.
	G8_IO4 IOSCR = 0x01 << 31 //+ GROUP8_IO4 sampling mode.
)

const (
	G1_IO1n = 0
	G1_IO2n = 1
	G1_IO3n = 2
	G1_IO4n = 3
	G2_IO1n = 4
	G2_IO2n = 5
	G2_IO3n = 6
	G2_IO4n = 7
	G3_IO1n = 8
	G3_IO2n = 9
	G3_IO3n = 10
	G3_IO4n = 11
	G4_IO1n = 12
	G4_IO2n = 13
	G4_IO3n = 14
	G4_IO4n = 15
	G5_IO1n = 16
	G5_IO2n = 17
	G5_IO3n = 18
	G5_IO4n = 19
	G6_IO1n = 20
	G6_IO2n = 21
	G6_IO3n = 22
	G6_IO4n = 23
	G7_IO1n = 24
	G7_IO2n = 25
	G7_IO3n = 26
	G7_IO4n = 27
	G8_IO1n = 28
	G8_IO2n = 29
	G8_IO3n = 30
	G8_IO4n = 31
)

const (
	G1_IO1 IOCCR = 0x01 << 0  //+ GROUP1_IO1 channel mode.
	G1_IO2 IOCCR = 0x01 << 1  //+ GROUP1_IO2 channel mode.
	G1_IO3 IOCCR = 0x01 << 2  //+ GROUP1_IO3 channel mode.
	G1_IO4 IOCCR = 0x01 << 3  //+ GROUP1_IO4 channel mode.
	G2_IO1 IOCCR = 0x01 << 4  //+ GROUP2_IO1 channel mode.
	G2_IO2 IOCCR = 0x01 << 5  //+ GROUP2_IO2 channel mode.
	G2_IO3 IOCCR = 0x01 << 6  //+ GROUP2_IO3 channel mode.
	G2_IO4 IOCCR = 0x01 << 7  //+ GROUP2_IO4 channel mode.
	G3_IO1 IOCCR = 0x01 << 8  //+ GROUP3_IO1 channel mode.
	G3_IO2 IOCCR = 0x01 << 9  //+ GROUP3_IO2 channel mode.
	G3_IO3 IOCCR = 0x01 << 10 //+ GROUP3_IO3 channel mode.
	G3_IO4 IOCCR = 0x01 << 11 //+ GROUP3_IO4 channel mode.
	G4_IO1 IOCCR = 0x01 << 12 //+ GROUP4_IO1 channel mode.
	G4_IO2 IOCCR = 0x01 << 13 //+ GROUP4_IO2 channel mode.
	G4_IO3 IOCCR = 0x01 << 14 //+ GROUP4_IO3 channel mode.
	G4_IO4 IOCCR = 0x01 << 15 //+ GROUP4_IO4 channel mode.
	G5_IO1 IOCCR = 0x01 << 16 //+ GROUP5_IO1 channel mode.
	G5_IO2 IOCCR = 0x01 << 17 //+ GROUP5_IO2 channel mode.
	G5_IO3 IOCCR = 0x01 << 18 //+ GROUP5_IO3 channel mode.
	G5_IO4 IOCCR = 0x01 << 19 //+ GROUP5_IO4 channel mode.
	G6_IO1 IOCCR = 0x01 << 20 //+ GROUP6_IO1 channel mode.
	G6_IO2 IOCCR = 0x01 << 21 //+ GROUP6_IO2 channel mode.
	G6_IO3 IOCCR = 0x01 << 22 //+ GROUP6_IO3 channel mode.
	G6_IO4 IOCCR = 0x01 << 23 //+ GROUP6_IO4 channel mode.
	G7_IO1 IOCCR = 0x01 << 24 //+ GROUP7_IO1 channel mode.
	G7_IO2 IOCCR = 0x01 << 25 //+ GROUP7_IO2 channel mode.
	G7_IO3 IOCCR = 0x01 << 26 //+ GROUP7_IO3 channel mode.
	G7_IO4 IOCCR = 0x01 << 27 //+ GROUP7_IO4 channel mode.
	G8_IO1 IOCCR = 0x01 << 28 //+ GROUP8_IO1 channel mode.
	G8_IO2 IOCCR = 0x01 << 29 //+ GROUP8_IO2 channel mode.
	G8_IO3 IOCCR = 0x01 << 30 //+ GROUP8_IO3 channel mode.
	G8_IO4 IOCCR = 0x01 << 31 //+ GROUP8_IO4 channel mode.
)

const (
	G1_IO1n = 0
	G1_IO2n = 1
	G1_IO3n = 2
	G1_IO4n = 3
	G2_IO1n = 4
	G2_IO2n = 5
	G2_IO3n = 6
	G2_IO4n = 7
	G3_IO1n = 8
	G3_IO2n = 9
	G3_IO3n = 10
	G3_IO4n = 11
	G4_IO1n = 12
	G4_IO2n = 13
	G4_IO3n = 14
	G4_IO4n = 15
	G5_IO1n = 16
	G5_IO2n = 17
	G5_IO3n = 18
	G5_IO4n = 19
	G6_IO1n = 20
	G6_IO2n = 21
	G6_IO3n = 22
	G6_IO4n = 23
	G7_IO1n = 24
	G7_IO2n = 25
	G7_IO3n = 26
	G7_IO4n = 27
	G8_IO1n = 28
	G8_IO2n = 29
	G8_IO3n = 30
	G8_IO4n = 31
)

const (
	G1E IOGCSR = 0x01 << 0  //+ Analog IO GROUP1 enable.
	G2E IOGCSR = 0x01 << 1  //+ Analog IO GROUP2 enable.
	G3E IOGCSR = 0x01 << 2  //+ Analog IO GROUP3 enable.
	G4E IOGCSR = 0x01 << 3  //+ Analog IO GROUP4 enable.
	G5E IOGCSR = 0x01 << 4  //+ Analog IO GROUP5 enable.
	G6E IOGCSR = 0x01 << 5  //+ Analog IO GROUP6 enable.
	G7E IOGCSR = 0x01 << 6  //+ Analog IO GROUP7 enable.
	G8E IOGCSR = 0x01 << 7  //+ Analog IO GROUP8 enable.
	G1S IOGCSR = 0x01 << 16 //+ Analog IO GROUP1 status.
	G2S IOGCSR = 0x01 << 17 //+ Analog IO GROUP2 status.
	G3S IOGCSR = 0x01 << 18 //+ Analog IO GROUP3 status.
	G4S IOGCSR = 0x01 << 19 //+ Analog IO GROUP4 status.
	G5S IOGCSR = 0x01 << 20 //+ Analog IO GROUP5 status.
	G6S IOGCSR = 0x01 << 21 //+ Analog IO GROUP6 status.
	G7S IOGCSR = 0x01 << 22 //+ Analog IO GROUP7 status.
	G8S IOGCSR = 0x01 << 23 //+ Analog IO GROUP8 status.
)

const (
	G1En = 0
	G2En = 1
	G3En = 2
	G4En = 3
	G5En = 4
	G6En = 5
	G7En = 6
	G8En = 7
	G1Sn = 16
	G2Sn = 17
	G3Sn = 18
	G4Sn = 19
	G5Sn = 20
	G6Sn = 21
	G7Sn = 22
	G8Sn = 23
)

const (
	CNT IOGXCR = 0x3FFF << 0 //+ CNT[13:0] bits (Counter value).
)

const (
	CNTn = 0
)
